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is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 1 mc003-1d 11/19/98 issi issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1998, integrated silicon solution, inc. is80c51 is80c31 cmos single chip 8-bit microcontroller november 1998 features ? 80c51 based architecture ? 4k x 8 rom (is80c51 only) ? 128 x 8 ram ? two 16-bit timer/counters ? full duplex serial channel ? boolean processor ? four 8-bit i/o ports, 32 i/o lines ? memory addressing capability C 64k rom and 64k ram ? power save modes: C idle and power-down ? six interrupt sources ? most instructions execute in 0.3 m s ? cmos and ttl compatible ? maximum speed: 40 mhz @ vcc = 5v ? industrial temperature available ? packages available: C 40-pin dip C 44-pin plcc C 44-pin pqfp general description the issi is80c51 and is80c31 are high-performance microcontrollers fabricated using high-density cmos technology. the cmos is80c51/31 is functionally compatible with the industry standard 80c51 microcontrollers. the is80c51/31 is designed with 4k x 8 rom (is80c51 only); 128 x 8 ram; 32 programmable i/o lines; a serial i/o port for either multiprocessor communications, i/o expansion or full duplex uart; two 16-bit timer/counters; a six-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. the is80c51/31 can be expanded using standard ttl compatible memory. figure 1. is80c51/31 pin configuration: 40-pin pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 gnd vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 issi
is80c51 is80c31 2 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1 p1.0 nc vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 index 43 65 2144 18 19 20 21 22 23 24 43 42 41 40 25 26 27 28 top view figure 2. is80c51/31 pin configuration: 44-pin plcc
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 3 mc003-1d 11/19/98 issi figure 3. is80c51/31 pin configuration: 44-pin pqfp wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1 p1.0 nc vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 42 41 44 43 40 39 38 12 13 14 15 16 17 18 37 36 35 34 19 20 21 22
is80c51 is80c31 4 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi figure 4. is80c51/31 block diagram pcon scon tmod tcon th0 tl0 th1 tl1 sbuf ie ip interrupt block serial port block timer block p3 drivers p3 latch psw timing and control oscillator xtal2 xtal1 instruction register p3.0-p3.7 p1 drivers p1 latch dptr buffer pc incrementer program counter program address register p1.0-p1.7 p2.0-p2.7 p0.0-p0.7 psen ale rst ea tmp2 alu acc stack point b register vcc ram addr register p2 latch p0 latch p2 drivers p0 drivers address decoder & 128 bytes ram address decoder & 4k rom tmp1
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 5 mc003-1d 11/19/98 issi table 1. detailed pin description symbol pdip plcc pqfp i/o name and function ale 30 33 27 i/o address latch enable: output pulse for latching the low byte of the address during an address to the external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ea 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 0fffh. p0.0-p0.7 39-32 43-36 37-30 i/o port 0: port 0 is an 8-bit open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pullups when emitting 1s. p1.0-p1.7 1-8 2-9 40-44 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal 1-3 pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). the port 1 output buffers can sink/source four ttl inputs. port 1 also receives the low-order address byte during rom verification. p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses (movx @ dptr). in this application, port 2 uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri [i = 0, 1]), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order bits and some control signals during rom verification.
is80c51 is80c31 6 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pullups. port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. (see dc characteristics: i il ). port 3 also serves the special features of the is80lv51/31, as listed below: 10 11 5 i rxd (p3.0): serial input port. 11 13 7 o txd (p3.1): serial output port. 12 14 8 i int0 int0 int0 int0 int0 (p3.2): external interrupt 0. 13 15 9 i int1 int1 int1 int1 int1 (p3.3): external interrupt 1. 14 16 10 i t0 (p3.4): timer 0 external input. 15 17 11 i t1 (p3.5): timer 1 external input. 16 18 12 o wr wr wr wr wr (p3.6): external data memory write strobe. 17 19 13 o rd rd rd rd rd (p3.7): external data memory read strobe. psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal mos resistor to gnd permits a power-on reset using only an external capacitor connected to vcc. xtal 1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal 2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. gnd 20 22 16 i ground: 0v reference. vcc 40 44 38 i power supply: this is the power supply voltage for operation. table 1. detailed pin description (continued) symbol pdip plcc pqfp i/o name and function
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 7 mc003-1d 11/19/98 issi operating description the detail description of the is80c51/31 included in this description are: ? memory map and registers ? timer/counters ? serial interface ? interrupt system ? other information memory map and registers memory the is80c51/31 has separate address spaces for program and data memory. the program and data memory can be up to 64k bytes long. the lower 4k program memory can reside on-chip. (is80c51 only) figure 5 shows a map of the is80c51/31 program and data memory. the is80c51/31 has 128 bytes of on-chip ram, plus numbers of special function registers. the lower 128 bytes can be accessed either by direct addressing or by indirect addressing. figure 6 shows internal data memory organization and sfr memory map. the lower 128 bytes of ram can be divided into three segments as listed below and shown in figure 7. 1. register banks 0-3: locations 00h through 1fh (32 bytes). the device after reset defaults to register bank 0. to use the other register banks, the user must select them in software. each register bank contains eight 1-byte registers r0-r7. reset initial- izes the stack point to location 07h, and is incremented once to start from 08h, which is the first register of the second register bank. 2. bit addressable area: 16 bytes have been as- signed for this segment 20h-2fh. each one of the 128 bits of this segment can be directly addressed (0- 7fh). each of the 16 bytes in this segment can also be addressed as a byte. 3. scratch pad area: 30h-7fh are available to the user as data ram. however, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent sp data destruction. ffffh: 64k 0fffh: 4k program memory (read only) data memory (read/write) ea = 0 external external external psen ea = 1 internal 0000 00 ffffh internal ffh 80h 7fh 0000 rd wr figure 5. is80c51/31 program and data memory structure
is80c51 is80c31 8 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi special function registers the special function registers (sfr's) are located in upper 128 bytes direct addressing area. the sfr memory map in figure 6 shows that. not all of the addresses are occupied. unoccupied addresses are not implemented on the chip. read accesses to these addresses in general return random data, and write accesses have no effect. user software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. in that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1. the functions of the sfrs are outlined in the following sections, and detailed in table 2. accumulator (acc) acc is the accumulator register. the mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as a. b register (b) the b register is used during multiply and divide operations. for other instructions it can be treated as another scratch pad register. program status word (psw) . the psw register contains program status information. figure 6. internal data memory and sfr memory map accessible by direct addressing not available in is80c51/31 accessible by direct and indirect addressing 80h 7fh 0 ffh 80h upper 128 lower 128 special function registers ports, status and control bits, timer, registers, stack pointer, accumulator (etc.) b acc psw ip p3 ie p2 scon p1 tcon p0 bit addressable f8 f0 e8 e0 d8 d0 c8 c0 b8 b0 a8 a0 98 90 88 80 ff f7 ef e7 df d7 cf c7 bf b7 af a7 9f 97 8f 87 sbuf tmod sp tl0 dpl tl1 dph th0 th1 pcon figure 7. lower 128 bytes of internal ram 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 7f 77 6f 67 5f 57 4f 47 3f 37 2f 27 1f 17 0f 07 ...7f 0 ... bank3 bank2 bank 1 bank 0 8 bytes register banks bit addressable segment scratch pad area
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 9 mc003-1d 11/19/98 issi special function registers (continued) stack pointer (sp) the stack pointer register is eight bits wide. it is incremented before data is stored during push and call executions. while the stack may reside anywhere in on- chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at location 08h. data pointer (dptr) the data pointer consists of a high byte (dph) and a low byte (dpl). its function is to hold a 16-bit address. it may be manipulated as a 16-bit register or as two independent 8-bit registers. ports 0 to 3 p0, p1, p2, and p3 are the sfr latches of ports 0, 1, 2, and 3, respectively. serial data buffer (sbuf) the serial data buffer is actually two separate registers, a transmit buffer and a receive buffer register. when data is moved to sbuf, it goes to the transmit buffer, where it is held for serial transmission. (moving a byte to sbuf initiates the transmission.) when data is moved from sbuf, it comes from the receive buffer. timer registers register pairs (th0, tl0) and (th1, tl1) are the 16-bit counter registers for timer/counters 0 and 1, respectively. control registers special function registers ip, ie, tmod, tcon, scon, and pcon contain control and status bits for the interrupt system, the timer/counters, and the serial port. they are described in later sections of this chapter.
is80c51 is80c31 10 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi table 2. special function register symbol description direct address bit address, symbol, or alternative port function reset value acc (1) accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b (1) b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dph data pointer (dptr) high 83h 00h dpl data pointer (dptr) low 82h 00h af ae ad ac ab aa a9 a8 ie (1) interrupt enable a8h ea es et1 ex1 et0 ex0 0xx00000b bf be bd bc bb ba b9 b8 ip (1) interrupt priority b8h ps pt1 px1 pt0 px0 xxx00000b 87 86 85 84 83 82 81 80 p0 (1) port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 97 96 95 94 93 92 91 90 p1 (1) port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2 (1) port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 b7 b6 b5 b4 b3 b2 b1 b0 p3 (1) port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh rd wr t1 t0 int1 int0 txd rxd pcon power control 87h smod gf1 gf0 pd idl 0xxx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw (1) program status word d0h cy ac f0 rs1 rs0 ov p 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon (1) serial controller 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon (1) timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tmod timer mode 89h gate c/ t m1 m0 gate c/ t m1 m0 00h th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h note: 1. denotes bit addressable.
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 11 mc003-1d 11/19/98 issi the detail description of each bit is as follows: psw: program status word. bit addressable. 76543210 cy ac f0 rs1 rs0 ov p register description: cy psw.7 carry flag. ac psw.6 auxiliary carry flag. f0 psw.5 flag 0 available to the user for general purpose. rs1 psw.4 register bank selector bit 1. (1) rs0 psw.3 register bank selector bit 0. (1) ov psw.2 overflow flag. psw.1 usable as a general purpose flag p psw.0 parity flag. set/clear by hardware each instruction cycle to indicate an odd/even number of 1 bits in the accumulator. note: 1. the value presented by rs0 and rs1 selects the corre- sponding register bank. rs1 rs0 register bank address 0 0 0 00h-07h 0 1 1 08h-0fh 1 0 2 10h-17h 1 1 3 18h-1fh pcon: power control register. not bit addressable. 76543210 smod gf1 gf0 pd idl register description: smod double baud rate bit. if timer 1 is used to generate baud rate and smod=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. not implemented, reserve for future use. (1) not implemented, reserve for future use. (1) not implemented, reserve for future use. (1) gf1 general purpose flag bit. gf0 general purpose flag bit. pd power-down bit. setting this bit activates power- down mode. idl idle mode bit. setting this bit activates idle mode. if 1s are written to pd and idl at the same time, pd takes precedence. note: 1. user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. ie: interrupt enable register. bit addressable. 76543210 ea es et1 ex1 et0 ex0 register description: ea ie.7 disable all interrupts. if ea=0, no interrupt will be acknowledged. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ie.6 not implemented, reserve for future use. (5) ie.5 not implemented, reserve for future use. (5) es ie.4 enable or disable the serial port interrupt. et1 ie.3 enable or disable the timer 1 overflow interrupt. ex1 ie.2 enable or disable external interrupt 1. et0 ie.1 enable or disable the timer 0 overflow interrupt. ex0 ie.0 enable or disable external interrupt 0. note: to use any of the interrupts in the 80c51 family, the following three steps must be taken: 1. set the ea (enable all) bit in the ie register to 1. 2. set the coresponding individual interrupt enable bit in the ie register to 1. 3. begin the interrupt service routine at the corresponding vector address of that interrupt (see below). interrupt source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri & ti 0023h 4. in addition, for external interrupts, pins int0 and int1 (p3.2 and p3.3) must be set to 1, and depending on whether the interrupt is to be level or transition acti- vated, bits it0 or it1 in the tcon register may need to be set to 0 or 1. itx = 0 level activated (x = 0, 1) itx = 1 transition activated 5. user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features.
is80c51 is80c31 12 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi ip: interrupt priority register. bit addressable. 76543210 ps pt1 px1 pt0 px0 register description: ip.7 not implemented, reserve for future use (3) ip.6 not implemented, reserve for future use (3) ip.5 not implemented, reserve for future use (3) ps ip.4 defines serial port interrupt priority level pt1 ip.3 defines timer 1 interrupt priority level px1 ip.2 defines external interrupt 1 priority level pt0 ip.1 defines timer 0 interrupt priority level px0 ip.0 defines external interrupt 0 priority level notes: 1. in order to assign higher priority to an interrupt the coresponding bit in the ip register must be set to 1. while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt. 2. priority within level is only to resolve simultaneous requests of the same priority level. from high to low, interrupt sources are listed below: ie0 tf0 ie1 tf1 ri or ti 3. user software should not write 1s to reserved bits. these bits may be used in future products to invoke new features. tcon: timer/counter control register. bit addressable 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 register description: tf1 tcon.7 timer 1 overflow flag. set by hardware when the timer/counter 1 overflows. cleared by hardware as processor vectors to the interrupt service routine. tr1 tcon.6 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/ off. tf0 tcon.5 timer 0 overflow flag. set by hardware when the timer/counter 0 overflows. cleared by hardware as processor vectors to the interrupt service routine. tr0 tcon.4 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/ off. ie1 tcon.3 external interrupt 1 edge flag. set by hardware when the external interrupt edge is detected. cleared by hardware when interrupt is processed. it1 tcon.2 interrupt 1 type control bit. set/cleared by software specify falling edge/low level triggered external interrupt. ie0 tcon.1 external interrupt 0 edge flag. set by hardware when the external interrupt edge is detected. cleared by hardware when interrupt is processed. it0 tcon.0 interrupt 0 type control bit. set/cleared by software specify falling edge/low level triggered external interrupt.
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 13 mc003-1d 11/19/98 issi tmod: timer/counter mode control register. not bit addressable. timer 1 timer 0 gate c/ t t t t t m1 m0 gate c/ t t t t t m1 m0 gate when trx (in tcon) is set and gate=1, timer/ counterx will run only while intx pin is high (hardware control). when gate=0, timer/ counterx will run only while trx=1 (software control). c/ t timer or counter selector. cleared for timer operation (input from internal system clock). set for counter operation (input from tx input pin). m1 mode selector bit. (1) m0 mode selector bit. (1) note 1: m1 m0 operating mode 0 0 mode 0. (13-bit timer) 0 1 mode 1. (16-bit timer/counter) 1 0 mode 2. (8-bit auto-load timer/counter) 1 1 mode 3. (splits timer 0 into tl0 and th0. tl0 is an 8-bit timer/counter controller by the standard timer 0 control bits. th0 is an 8-bit timer and is controlled by timer 1 control bits.) 1 1 mode 3. (timer/counter 1 stopped). scon: serial port control register. bit addressable. 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri register description: sm0 scon.7 serial port mode specifier. (1) sm1 scon.6 serial port mode specifier. (1) sm2 scon.5 enable the multiprocessor com- munication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1 then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if valid stop bit was not received. in mode 0, sm2 should be 0. ren scon.4 set/cleared by software to enable/ disable reception. tb8 scon.3 the 9th bit that will be transmitted in mode 2 and 3. set/cleared by software. rb8 scon.2 in modes 2 and 3, rb8 is the 9th data bit that was received. in mode 1, if sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti scon.1 transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. must be cleared by software. ri scon.0 receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see sm2). must be cleared by software. note: sm0 sm1 mode description baud rate 0 0 0 shift register fosc/12 0 1 1 8-bit uart variable 1 0 2 9-bit uart fosc/64 or fosc/32 1 1 3 9-bit uart variable
is80c51 is80c31 14 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi timer/counters the is80c51/31 has two 16-bit timer/counter registers: timer 0 and timer 1. both can be configured to operate either as timers or event counters. as a timer, the register is incremented every machine cycle. thus, the register counts machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. as a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 and t1. the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. in addition to the timer or counter functions, timer 0 and timer 1 have four operating modes: (13-bit timer, 16-bit timer, 8-bit auto-reload, split timer). timer 0 and timer 1 timer/counters 0 and 1 are present in both the is80c51/ 31 and is80c52/32. the timer or counter function is selected by control bits c/ t in the special function regiser tmod. these two timer/counters have four operating modes, which are selected by bit pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timer/counters, but mode 3 is different. the four modes are described in the following sections. mode 0: both timers in mode 0 are 8-bit counters with a divide-by- 32 prescaler. figure 8 shows the mode 0 operation as it applies to timer 1. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf1. the counted input is enabled to the timer when tr1 = 1 and either gate = 0 or int1 = 1. setting gate = 1 allows the timer to be controlled by external input int1 , to facilitate pulse width measurements. tr1 is a control bit in the special function register tcon. gate is in tmod. the 13-bit register consists of all eight bits of th1 and the lower five bits of tl1. the upper three bits of tl1 are indeterminate and should be ignored. setting the run flag (tr1) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1, except that tr0, tf0 and int0 replace the corresponding timer 1 signals in figure 7. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). timer clock tl1 (8 bits) th1 (8 bits) tf1 overflow flag figure 9. timer/counter 1 mode 1: 16-bit counter divide 12 osc osc (xtal2) tl1 (5 bits) th1 (8 bits) tf1 control c/t = 0 c/t = 1 gate int1 pin tr1 t1 pin interrupt p1 s1 s2 s3 one machine cycle one machine cycle s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 figure 8. timer/counter 1 mode 0: 13-bit counter
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 15 mc003-1d 11/19/98 issi divide 12 1/12 fosc 1/12 fosc osc tl0 (8 bits) tf0 tf1 control control c/t = 0 c/t = 1 gate tr1 int0 pin tr0 t0 pin interrupt th0 (8 bits) interrupt 1/12 fosc divide 12 osc tl1 (8 bits) th1 (8 bits) tf1 control reload c/t = 0 c/t = 1 gate int0 pin tr1 t1 pin interrupt mode 1: mode 1 is the same as mode 0, except that the timer register is run with all 16 bits. the clock is applied to the combined high and low timer registers (tl1/th1). as clock pulses are received, the timer counts up: 0000h, 0001h, 0002h, etc. an overflow occurs on the ffffh-to-0000h overflow flag. the timer continues to count. the overflow flag is the tf1 bit in tcon that is read or written by software (see figure 9). mode 2: mode 2 configures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in figure 10. overflow from tl1 not only sets tf1, but also reloads tl1 with the contents of th1, which is preset by software. the reload leaves the th1 unchanged. mode 2 operation is the same for timer/counter 0. mode 3: timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 11. tl0 uses the timer 0 control bits: c/ t , gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is for applications requiring an extra 8-bit timer or counter. with timer 0 in mode 3, the is80c51/31 can appear to have three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3. in this case, timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. figure 11. timer/counter 0 mode 3: two 8-bit counters figure 10. timer/counter 1 mode 2: 8-bit auto-reload
is80c51 is80c31 16 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi table 5. timer/counter 1 used as a timer tmod mode timer 1 internal external function control (1) control (2) 0 13-bit timer 00h 80h 1 16-bit timer 10h 90h 2 8-bit auto-reload 20h a0h 3 does not run 30h b0h table 6. timer/counter 1 used as a counter tmod mode timer 1 internal external function control (1) control (2) 0 13-bit timer 40h c0h 1 16-bit timer 50h d0h 2 8-bit auto-reload 60h e0h 3 not available notes: 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on/off by the 1-to-0 transition on int1 (p3.3) when tr1 = 1 (hardware control). timer setup tables 3 through 6 give tmod values that can be used to set up timers in different modes. it assumes that only one timer is used at a time. if timers 0 and 1 must run simultaneously in any mode, the value in tmod for timer 0 must be ored with the value shown for timer 1 (tables 5 and 6). for example, if timer 0 must run in mode 1 gate (external control), and timer 1 must run in mode 2 counter, then the value that must be loaded into tmod is 69h (09h from table 3 ored with 60h from table 6). moreover, it is assumed that the user is not ready at this point to turn the timers on and will do so at another point in the program by setting bit trx (in tcon) to 1. table 3. timer/counter 0 used as a timer tmod mode timer 0 internal external function control (1) control (2) 0 13-bit timer 00h 08h 1 16-bit timer 01h 09h 2 8-bit auto-reload 02h 0ah 3 two 8-bit timers 03h 0bh table 4. timer/counter 0 used as a counter tmod mode timer 0 internal external function control (1) control (2) 0 13-bit timer 04h 0ch 1 16-bit timer 05h 0dh 2 8-bit auto-reload 06h 0eh 3 one 8-bit counter 07h 0fh notes: 1. the timer is turned on/off by setting/clearing bit tr0 in the software. 2. the timer is turned on/off by the 1-to-0 transition on int0 (p3.2) when tr0 = 1 (hardware control).
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 17 mc003-1d 11/19/98 issi serial interface the serial port is full duplex, which means it can transmit and receive simultaneously. it is also receive-buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (however, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in the following four modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted/received, with the lsb first. the baud rate is fixed at 1/12 the oscillator frequency (see figure 12). mode 1: ten bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable (see figure 13). mode 2: eleven bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), a programmable ninth data bit, and a stop bit (1). on transmit, the ninth data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) can be moved into tb8. on receive, the ninth data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (see figure 14). mode 3: eleven bits are transmitted (through txd) or received (through rxd): a start bit (0), eight data bits (lsb first), a programmable ninth data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except the baud rate, which is variable in mode 3 (see figure 15). in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, nine data bits are received, followed by a stop bit. the ninth bit goes into rb8; then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. the following example shows how to use the serial interrupt for multiprocessor communications. when the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. an address byte differs from a data byte in that the ninth bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave is interrupted by a data byte. an address byte, however, interrupts all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave clears its sm2 bit and prepares to receive the data bytes that follows. the slaves that are not addressed set their sm2 bits and ignore the data bytes. sm2 has no effect in mode 0 but can be used to check the validity of the stop bit in mode 1. in a mode 1 reception, if sm2 = 1, the receive interrupt is not activated unless a valid stop bit is received. baud rates the baud rate in mode 0 is fixed as shown in the following equation. mode 0 baud rate = oscillator frequency 12 the baud rate in mode 2 depends on the value of the smod bit in special function register pcon. if smod = 0 (the value on reset), the baud rate is 1/64 of the oscillator frequency. if smod = 1, the baud rate is 1/32 of the oscillator frequency, as shown in the following equation. mode 2 baud rate = 2 smod x (oscillator frequency) 64 in the is80c51/31, the timer 1 overflow rate determines the baud rates in modes 1 and 3.
is80c51 is80c31 18 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi using the timer 1 to generate baud rates when timer 1 is the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod according to the following equation. mode 1, 3 2 smod x (timer 1 overflow rate) baud rate = 32 the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation in any of its 3 running modes. in the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of tmod = 0010b). in this case, the baud rate is given by the following formula. mode 1,3 2 smod x oscillator frequency baud rate = 32 12x [256-(th1)] programmers can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. table 7 lists commonly used baud rates and how they can be obtained from timer 1. table 7. commonly used baud rates generated by timer 1 timer 1 baud rate f osc smod c/ t t t t t mode reload value mode 0 max: 1 mhz 12 mhz x x x x mode 2 max: 375k 12 mhz 1 x x x modes 1, 3: 62.5k 12 mhz 1 0 2 ffh 19.2k 11.059 mhz 1 0 2 fdh 9.6k 11.059 mhz 0 0 2 fdh 4.8k 11.059 mhz 0 0 2 fah 2.4k 11.059 mhz 0 0 2 f4h 1.2k 11.059 mhz 0 0 2 e8h 137.5 11.986 mhz 0 0 2 1dh 110 6 mhz 0 0 2 72h 110 12 mhz 0 0 1 feebh more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted/received, with the lsb first. the baud rate is fixed at 1/12 the oscillator frequency. figure 12 shows a simplified functional diagram of the serial port in mode 0 and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to sbuf" signal at s6p2 also loads a 1 into the ninth position of the transmit shift register and tells the tx control block to begin a transmission. the internal timing is such that one full machine cycle will elapse between "write to sbuf" and activation of send. send transfer the output of the shift register to the alternate output function line of p3.0, and also transfers shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift register are shifted one position to the right. as data bits shift out to the right, 0s come in from the left. when the msb of the data byte is at the output position of the shift register, the 1 that was initially loaded into the ninth position is just to the left of the msb, and all positions to the left of that contain 0s. this condition flags the tx control block to do one last shift, then deactivate send and set ti. both of these actions occur at s1p1 of the tenth machine cycle after "write to sbuf."
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 19 mc003-1d 11/19/98 issi reception is initiated by the condition ren = 1 and ri = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register and activates receive in the next clock phase. receive enables shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are shifted on position to the left. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared and ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), eight data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the is80c51/31 the baud rate is determined by the timer 1 overflow rate. figure 13 shows a simplified functional diagram of the serial port in mode 1 and associated timings for transmit and receive. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to =sbuf" signal also loads a 1 into the ninth bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to sbuf" signal. the transmission begins when send is activated, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, 0s are clocked in from the left. when the msb of the data byte is at the output position of the shift register, the 1 that was initially loaded into the ninth position is just to the left of the msb, and all positions to the left of that contain 0s. this condition flags the tx control unit to do one last shift, then deactivate send and set ti. this occurs at the tenth divide-by-16 rollover after "write to sbuf". reception is initiated by a 1-to-0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times the established baud rate. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16. at the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least two of the three samples. this is done to reject noise. in order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. if the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. as data bits come in from the right, 1s shift to the left. when the start bit arrives at the leftmost position in the shift register, (which is a 9-bit register in mode 1), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1) ri = 0 and 2) either sm2 = 0, or the received stop bit =1 if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the eight data bits go into sbuf, and ri is activated. at this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), eight data bits (lsb first), a programmable ninth data bit, and a stop bit (1). on transmit, the ninth data bit (tb8) can be assigned the value of 0 or 1. on receive, the ninth data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1. figures 14 and 15 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the ninth bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the "write to sbuf" signal also loads tb8 into the ninth bit position of the transmit shift
is80c51 is80c31 20 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi table 8. serial port setup mode scon sm2variation 0 10h 1 50h 2 90h 3 d0h 0na 1 70h 2 b0h 3 f0h single processor environment (sm2 = 0) multiprocessor environment (sm2 = 1) register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by- 16 counter. thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to sbuf" signal. the transmission begins when send is activated, which puts the start bit at txd. one bit timer later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the ninth bit position of the shift register. thereafter, only 0s are clocked in. thus, as data bits shift out to the right, 0s are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain 0s. this condition flags the tx control unit to do one last shift, then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after "write to sbuf". reception is initiated by a 1-to-0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times the established baud rate. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least two of the three samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. as data bits come in from the right, is shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) ri = 0, and 2) either sm2 = 0 or the received 9th data bit = 1 if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received ninth data bit goes into rb8, and the first eight data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit continues looking for a 1-to-0 transition at the rxd input. note that the value of the received stop bit is irrelevant to sbuf, rb8, or ri.
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 21 mc003-1d 11/19/98 issi figure 12. serial port mode 0 write to sbuf load sbuf ren ri sbuf zero detector shift shift rxd p3.0 alt output function txd p3.1 alt output function rxd p3.0 alt input function q s d cl start tx clock rx clock start shift send receive shift tx control s6 serial port interrupt shift clock ri rx control 1 1 1 1 1 1 1 0 input shift reg. sbuf is80c51/31 internal bus read sbuf is80c51/31 internal bus s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 ale send shift shift ti rxd (d out ) txd (shift clock) write to sbuf s6p2 s5p2 s6p1 s3p1 d0 d1 d2 d3 d5 d6 d7 d4 ri receive rxd (d in ) txd (shift clock) write to scon (clear ri) d0 d1 d2 d3 d5 d6 d7 d4 transmit receive
is80c51 is80c31 22 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi figure 13. serial port mode 1 write to sbuf load sbuf bit detector input shift reg. (9 bits) sample rclk "0" "0" "1" "1" tclk smod = 1 smod = 0 sbuf zero detector shift rxd txd q s d cl start rx clock rx clock start data send load sbuf shift 1ffh tx control serial port interrupt ri rx control sbuf is80c51/31 internal bus read sbuf s1p1 d0 d1 d2 d3 d5 d6 d7 d4 d0 d1 d2 d3 d5 d6 d7 d4 send data shift shift tx clock write to sbuf transmit receive shift ti 16 16 1-to-0 transition detector is80c51/31 internal bus timer 1 overflow timer 2 overflow 2 tb8 stop bit stop bit start bit start bit txd rxd bit detector sample times ti ri rx clock 16 reset
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 23 mc003-1d 11/19/98 issi figure 14. serial port mode 2 write to sbuf load sbuf bit detector input shift reg. (9 bits) sample mode 2 (smod is pcon. 7) sbuf zero detector shift rxd txd q s d cl start tx clock start data send load sbuf shift 1ffh tx control serial port interrupt ri rx control sbuf is80c51/31 internal bus read sbuf s1p1 d0 d1 d2 d3 d5 d6 d7 tb8 d4 send data shift shift tx clock write to sbuf transmit receive shift ti 16 16 1-to-0 transition detector is80c51/31 internal bus phase 2 clock (1/2 f osc ) 2 tb8 stop bit txd bit detector sample times ti ri stop bit gen stop bit gen rx clock smod 0 smod 1 d0 d1 d2 d3 d5 d6 d7 d4 stop bit rxd rx clock 16 reset rb8 start bit start bit
is80c51 is80c31 24 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi figure 15. serial port mode 3 shift receive bit detector sample times ri d0 d1 d2 d3 d5 d6 d7 d4 stop bit rxd rx clock 16 reset rb8 write to sbuf load sbuf bit detector input shift reg. (9 bits) sample rclk "0" "0" "1" "1" tclk smod = 1 smod = 0 sbuf zero detector shift rxd txd q s d cl start tx clock rx clock start data send load sbuf shift 1ffh tx control serial port interrupt ri rx control sbuf is80c51/31 internal bus read sbuf s1p1 d0 d1 d2 d3 d5 d6 tb8 d7 d4 send data shift tx clock write to sbuf transmit shift ti 16 16 1-to-0 transition detector is80c51/31 internal bus timer 1 overflow timer 2 overflow 2 tb8 stop bit txd ti stop bit gen start bit start bit
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 25 mc003-1d 11/19/98 issi interrupt system the is80c51/31 provides 6 interrupt sources: two external interrupts, three timer interrupts, and a serial port interrupt. these are shown in figure 16. the external interrupts int0 and int1 can each be either level-activated or transition-activated, depending on bits it0 and it1 in register tcon. the flags that actually generate these interrupts are the ie0 and ie1 bits in tcon. when the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated. if the interrupt was level-activated, then the external requesting source (rather than the on-chip hardware) controls the request flag. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers (except for timer 0 in mode 3). when a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. the serial port interrupt is generated by the logical or of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine normally must determine whether ri or ti generated the interrupt, and the bit must be cleared in software. all of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. that is, interrupts can be generated and pending interrupts can be canceled in software. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie (interrupt enable) at address 0a8h. as well as individual enable bits for each interrupt source, there is a global enable/disable bit that is cleared to disable all interrupts or set to turn on interrupts (see sfr ie). figure 16. interrupt system int1 internal serial port scon.0 ri scon.1 ti timer/counter 1 tcon.7 tf1 external int rqst 1 tcon.3 ie1 timer/counter 0 tcon.5 tf0 external int rqst 0 tcon.1 ie0 int0 ie.4 ie.3 et1 ie.2 ex1 ie.1 et0 ie.0 ex0 ie.7 ip.4 ps ea ip.3 pt1 ip.2 px1 ip.1 pt0 ip.0 px0 polling hardware source i.d. high priority interrupt request vector source i.d. low priority interrupt request vector es
is80c51 is80c31 26 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi priority level structure each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in special function register ip (interrupt priority) at address 0b8h. ip is cleared after a system reset to place all interrupts at the lower priority level by default. a low- priority interrupt can be interrupted by a high-priority interrupt but not by another low-priority interrupt. a high- priority interrupt can not be interrupted by any other interrupt source. if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level there is a second priority structure determined by the polling sequence, as follows: source priority within level 1. ie0 (highest) 2. tf0 3. ie1 4. tf1 5. ri + ti (lowest) note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level . how interrupts are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware generated lcall is not blocked by any of the following conditions: 1. an interrupt of equal or higher priority level is already in progress. 2. the current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. the instruction in progress is reti or any write to the ie or ip registers. any of these three conditions will block the generation of the lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie or ip, then at least one more instruction will be executed before any interrupt is vectored to. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cycle. if an active interrupt flag is not being serviced because of one of the above conditions and is not still active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the polling cycle/lcall sequence is illustrated in figure 17. note that if an interrupt of higher priority level goes active prior to s5p2 of the machine cycle labeled c3 in figure 17, then in accordance with the above rules it will be serviced during c5 and c6, without any instruction of the lower priority routine having been executed. figure 17. interrupt response timing diagram interrupt goes active interrupts are polled interrupt routine long call to interrupt vector address interrupt latched c4 c3 c2 c1 c5 s5p2 s6 e
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 27 mc003-1d 11/19/98 issi thus, the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate servicing routine. in some cases it also clears the flag that generated the interrupt, and in other cases it does not. it never clears the serial port flag. this must be done in the user's software. the processor clears an external interrupt flag (ie0 or ie1) only if it was transition-activated. the hardware-generated lcall pushes the contents of the program counter onto the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being serviced, as shown in the following table. interrupt interrupt cleared by vector source request bits hardware address int0 ie0 no (level) 0003h yes (trans.) timer 0 tf0 yes 000bh int1 ie1 no (level) 0013h yes (trans.) timer 1 tf1 yes 001bh serial port ri, ti no 0023h system rst 0000h reset execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note that a simple ret instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. sfr register and interrupt flag bit position external 0 ie0 tcon.1 external 1 ie1 tcon.3 timer 1 tf1 tcon.7 timer 0 tf0 tcon.5 serial port ti scon.1 serial port ri scon.0 when an interrupt is accepted the following action occurs: 1. the current instruction completes operation. 2. the pc is saved on the stack. 3. the current interrupt status is saved internally. 4. interrupts are blocked at the level of the interrupts. 5. the pc is loaded with the vector address of the isr (interrupts service routine). 6. the isr executes. the isr executes and takes action in response to the interrupt. the isr finishes with reti (return from interrupt) instruction. this retrieves the old value of the pc from the stack and restores the old interrupt status. execution of the main program continues where it left off. external interrupts the external sources can be programmed to be level- activated or transition-activated by setting or clearing bit it1 or it0 in register tcon. if itx= 0, external interrupt x is triggered by a detected low at the intx pin. if itx = 1, external interrupt x is edge-triggered. in this mode if successive samples of the intx pin show a high in one cycle and a low in the next cycle, interrupt request flag iex in tcon is set. flag bit iex then requests the interrupt.
is80c51 is80c31 28 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. if the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag iex will be set. iex will be automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. response time the int0 and int1 levels are inverted and latched into the interrupt flags ie0 and ie1 at s5p2 of every machine cycle. similarly, the serial port flags ri and ti are set at s5p2. the values are not actually polled by the circuitry until the next machine cycle. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in which the timers overflow. the values are then polled by the circuitry in the next cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. the call itself takes two cycles. thus, a minimum of three complete machine cycles elapsed between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 17 shows response timings. a longer response time results if the request is blocked by one of the three previously listed conditions. if an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. if the instruction in progress is not in its final cycle, the additional wait time cannot be more than three cycles, since the longest instructions (mul and div) are only four cycles long. if the instruction in progress is reti or an access to ie or ip, the additional wait time cannot be more than five cycles (a maximum of one more cycle to complete the instruction in progress, plus four cycles to complete the next instruction if the instruction is mul or div). thus, in a single-interrupt system, the response time is always more than three cycles and less than nine cycles. single-step operation the is80c51/31 interrupt structure allows single-step execution with very little software overhead. as previously noted, an interrupt request will not be serviced while an interrupt of equal priority level is still in progress, nor will it be serviced after reti until at least one other instruction has been executed. thus, once an interrupt routine has been entered, it cannot be reentered until at least one instruction of the interrupted program is executed. one way to use this feature for single-step operation is to program one of the external interrupts (for example, int0) to be level-activated. the service routine for the interrupt will terminate with the following code: jnb p3.2,$ ;wait here till int0 goes high jb p3.2,$ ;now wait here till it goes low reti ;go back and execute one instruction if the int0 pin, which is also the p3.2 pin, is held normally low, the cpu will go right into the external interrupt 0 routine and stay there until int0 is pulsed (from low-to- high-to-low). then it will execute reti, go back to the task program, execute one instruction, and immediately reenter the external interrupt 0 routine to await the next pulsing of p3.2. one step of the task program is executed each time p3.2 is pulsed.
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 29 mc003-1d 11/19/98 issi table 9. reset values of the sfr's sfr name reset value pc 0000h acc 00h b 00h psw 00h sp 07h dptr 0000h p0Cp3 ffh ip xxx00000b ie 0xx00000b tmod 00h tcon 00h th0 00h tl0 00h th1 00h tl1 00h scon 00h sbuf indeterminate pcon 0xxx0000b other information reset the reset input is the rst pin, which is the input to a schmitt trigger. a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running . the cpu responds by generating an internal reset, with the timing shown in figure 18. the external reset signal is asynchronous to the internal clock. the rst pin is sampled during state 5 phase 2 of every machine cycle. the port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the rst pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the rst pin. the internal reset algorithm writes 0s to all the sfrs except the port latches, the stack pointer, and sbuf. the port latches are initialized to ffh, the stack pointer to 07h, and sbuf is indeterminate. table 9 lists the sfrs and their reset values. then internal ram is not affected by reset. on power-up the ram content is indeterminate. figure 18. reset timing 12 osc. periods ale rst sample rst sample rst internal reset signal psen p0 11 osc. periods inst addr inst inst inst 19 osc. periods s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 addr addr addr inst addr
is80c51 is80c31 30 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi power-on reset an automatic reset can be obtained when v cc goes through a 10 m f capacitor and gnd through an 8.2k resistor, providing the v cc rise time does not exceed 1 msec and the oscillator start-up time does not exceed 10 msec. for the is80c51/31, the external resistor can be removed because the rst pin has an internal pulldown. the capicator value can then be reduced to 1 m f (see figure 19). when power is turned on, the circuit holds the rst pin high for an amount of time that depends on the value of the capacitor and the rate at which it charges. to ensure a good reset, the rst pin must be high long enough to allow the oscillator time to start-up (normally a few msec) plus two machine cycles. note that the port pins will be in a random state until the oscillator has start and the internal reset algorithm has written 1s to them. with this circuit, reducing v cc quickly to 0 causes the rst pin voltage to momentarily fall below 0v. however, this voltage is internally limited, and will not harm the device. figure 19. power-on reset circuit vcc rst gnd vcc is80c51/31 1.0 f +
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 31 mc003-1d 11/19/98 issi power-saving modes of operation the is80c51/31 has two power-reducing modes. idle and power-down. the input through which backup power is supplied during these operations is vcc. figure 20 shows the internal circuitry which implements these features. in the idle mode (idl = 1), the oscillator continues to run and the interrupt, serial port, and timer blocks continue to be clocked, but the clock signal is gated off to the cpu. in power-down (pd = 1), the oscillator is frozen. the idle and power-down modes are activated by setting bits in special function register pcon. idle mode an instruction that sets pcon.0 is the last instruction executed before the idle mode begins. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to indicate whether an interrupt occurred during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset must be held active for only two machine cycles (24 oscillator periods) to complete the reset. the signal at the rst pin clears the idl bit directly and asynchronously. at this time, the cpu resumes program execution from where it left off; that is, at the instruction following the one that invoked the idle mode. as shown in figure 18, two or three machine cycles of program execution may take place before the internal reset algorithm takes control. on-chip hardware inhibits access to the internal ram during his time, but access to the port pins is not inhibited. to eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes idle should not write to a port pin or to external data ram. power-down mode an instruction that sets pcon.1 is the last instruction executed before power-down mode begins. in the power- down mode, the on-chip oscillator stops. with the clock frozen, all functions are stopped, but the on-chip ram and special function registers are held. the port pins output the values held by their respective sfrs. ale and psen output lows. in the power-down mode of operation, vcc can be reduced to as low as 2v. however, vcc must not be reduced before the power-down mode is invoked, and vcc must be restored to its normal operating level before the power-down mode is terminated. the reset that terminates power-down also frees the oscillator. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec). the only exit from power-down is a hardware reset. reset redefines all the sfrs but does not change the on-chip ram. osc clock gen pd xtal 2 xtal 1 idl cpu interrupt, serial port, timer blocks figure 20. idle and power-down hardware
is80c51 is80c31 32 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi table 10. status of the external pins during idle and power-down modes. mode memory ale psen psen psen psen psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data on-chip oscillators the on-chip oscillator circuitry of the is80c51/31 is a single stage linear inverter, intended for use as a crystal-controlled, positive reactance oscillator (figure 21). in this application the crystal is operated in its fundamental response mode as an inductive reactance in parallel resonance with capacitance external to the crystal (figure 24). examples of how to drive the clock with external oscillator are shown in figure 22. figure 21. oscillator connections the crystal specifications and capacitance values (c1 and c2 in figure 21) are not critical. 20 pf to 30 pf can be used in these positions at a12 mhz to 24 mhz frequency with good quality crystals. (for ranges greater than 24 mhz refer to figure 23.) a ceramic resonator can be used in place of the crystal in cost-sensitive applications. when a ceramic resonator is used, c1 and c2 are normally selected to be of somewhat higher values. the manufacturer of the ceramic resonator should be consulted for recommendation on the values of these capacitors. gnd xtal1 xtal2 external oscillator signal nc figure 22. external clock drive configuration c1 c2 gnd xtal1 xtal2
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 33 mc003-1d 11/19/98 issi figure 23. for high speed (> 24 mhz) note: when the frequency is higher than 24 mhz, please refer to table 11 for recommended value of c1, c2, and r. xtal2 xtal1 c1 c2 r table 11. recommended value for c1, c2, r frequency range 3.5 mhz - 24 mhz 30 mhz - 40 mhz c1 20 pf-30 pf 3 pf-10 pf c2 20 pf-30 pf 3 pf-10 pf r not apply 6.2k-10k
is80c51 is80c31 34 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi figure 24. rom verification rom verification the on-chip memory can be read out for rom verification. the address of the program memory location to be read is applied to port 1 and pins p2.3-p2.0. the other pins should be held at the verify level. the contents of the addressed locations will be emitted on port 0. external pullups are required on port 0 for this operation. figure 24 shows the setup to verify the program memory. xtal2 gnd xtal1 4-6 mhz p1 p2.3-p2.0 rst ea ale psen p2.7 p2.6 1 1 1 0 0 0 vcc p0 + 5v a7-a0 a11-a8 pgm data 10k x 8
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 35 mc003-1d 11/19/98 issi operating range (1) range ambient temperature v cc oscillator frequency commercial 0 c to +70 c 5v 10% 3.5 to 40 mhz industrial C40 c to +85 c 5v 10% 3.5 to 40 mhz note: 1. operating ranges define those limits between which the functionality of the device is guaranteed. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd (2) C2.0 to +7.0 v t bias temperature under bias (3) C40 to +85 c t stg storage temperature C65 to +125 c p t power dissipation 1.5 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C 2.0v for periods less than 20 ns. maximum dc voltage on output pins is vcc + 0.5v which may overshoot to vcc + 2.0v for periods less than 20 ns. 3. operating temperature is for commercial products only defined by this specification.
is80c51 is80c31 36 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi dc characteristics (t a = 0 c to 70 c; vcc = 5v 10%; gnd = 0v) symbol parameter test conditions min max unit v il input low voltage (all except ea ) C0.5 0.2vcc C 0.1 v v il 1 input low voltage ( ea ) C0.5 0.2vcc C 0.3 v v ih input high voltage 0.2vcc + 0.9 vcc + 0.5 v (all except xtal 1, rst) v ih 1 input high voltage (xtal 1) 0.7vcc vcc + 0.5 v v sch + rst positive schmitt-trigger 0.7vcc vcc + 0.5 v threshold voltage v sch C rst negative schmitt-trigger 0 0.2vcc v threshold voltage vol (1) output low voltage iol = 100 m a 0.3 v (ports 1, 2, 3) i ol = 1.6 ma 0.45 v i ol = 3.5 ma 1.0 v v ol 1 (1) output low voltage i ol = 200 m a 0.3 v (port 0, ale, psen )i ol = 3.2 ma 0.45 v i ol = 7.0 ma 1.0 v v oh output high voltage i oh = C10 m a 0.9vcc v (ports 1, 2, 3, ale, psen ) vcc = 4.5v-5.5v i ol = C25 m a 0.75vcc v i ol = C60 m a 2.4 v v oh 1 output high voltage i oh = C80 m a 0.9vcc v (port 0, ale, psen ) vcc = 4.5v-5.5v i oh = C300 m a 0.75vcc v i oh = C800 m a 2.4 v i il logical 0 input current (ports 1, 2, 3) v in = 0.45v C110 m a i li input leakage current (port 0) 0.45v < v in < vcc C10 +10 m a i tl logical 1-to-0 transition current v in = 2.0v C650 m a (ports 1, 2, 3) r rst rst pulldown resister 50 300 k w note: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink greater than the listed test conditions.
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 37 mc003-1d 11/19/98 issi power supply characteristics symbol parameter test conditions min max unit icc power supply current (1) vcc = 5.0v active mode 12 mhz 20 ma 16 mhz 26 ma 20 mhz 32 ma 24 mhz 38 ma 32 mhz 50 ma 40 mhz 62 ma idle mode 12 mhz 5 ma 16 mhz 6 ma 20 mhz 7.6 ma 24 mhz 9 ma 32 mhz 12 ma 40 mhz 15 ma power-down mode v cc = 5v 50 m a note: 1. see figures 25, 26, 27, and 28 for icc test conditiions. xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 xtal1 gnd nc rst vcc p0 ea vcc vcc icc xtal2 figure 25. active mode figure 26. idle mode xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 vcc figure 27. power-down mode
is80c51 is80c31 38 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi figure 28. icc test conditions 0.45v vcc ?0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ?0.1 ac characteristics (t a = 0 c to 70 c; vcc = 5v 10%; gnd = 0v; cl for port 0, ale and psen outputs = 100 pf; cl for other outputs = 80 pf) note: 1. clock signal waveform for icc tests in active and idle mode (t clch = t chcl = 5 ns) external memory characteristics 24 mhz 40 mhz variable oscillator clock clock (3.5 - 24 mhz) symbol parameter min max min max min max unit 1/t clcl oscillator frequency 3.5 24 mhz t lhll ale pulse width 43 40 2t clcl C40 ns t avll address valid to ale low 2 9 t clcl C40 ns t llax address hold after ale low 7 30 t clcl C35 ns t lliv ale low to valid instr in 105 70 3t clcl C20 ns t llpl ale low to psen low 2 15 t clcl C40 ns t plph psen pulse width 80 65 3t clcl C45 ns t pliv psen low to valid instr in 73 45 2t clcl C10 ns t pxix input instr hold after psen 0 0 0 ns t pxiz input instr float after psen 73 25 2t clcl C10 ns t aviv address to valid instr in 147 80 4t clcl C20 ns t plaz psen low to address float 10 5 10 ns t rlrh rd pulse width 150 100 6t clcl C100 ns t wlwh wr pulse width 150 100 6t clcl C100 ns t rldv rd low to valid data in 114 90 5t clcl C95 ns t rhdx data hold after rd 0 0 0 ns t rhdz data float after rd 63 50 2t clcl C70 ns t lldv ale low to valid data in 244 150 8t clcl C90 ns t avdv address to valid data in 285 180 9t clcl C90 ns t llwl ale low to rd or wr low 75 175 60 95 3t clcl C50 3t clcl +50 ns t avwl address to rd or wr low 77 65 4t clcl C90 ns t qvwx data valid to wr transition 2 10 t clcl C40 ns t whqx data hold after wr 2 10 t clcl C40 ns t qvwh data valid to wr high 219 165 7t clcl C70 ns t rlaz rd low to address float 63 0 2t clcl C20 ns t whlh rd or wr high to ale high 2 82 15 35 t clcl C40 t clcl +40 ns
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 39 mc003-1d 11/19/98 issi external memory characteristics (continued) 24 mhz 40 mhz variable oscillator clock clock (3.5 - 24 mhz) symbol parameter min max min max min max unit t xlxl serial port clock cycle time 500 250 12t clcl C10 ns t qvxh output data setup to 284 170 10t clcl C133 ns clock rising edge t xhqx output data hold after 33 33 2t clcl C50 ns clock rising edge t xhdx input data hold after 0 0 0 ns clock rising edge t xhdv clock rising edge to 284 117 10t clcl C133 ns input data valid external clock drive symbol parameter min max unit 1/t clcl oscillator frequency 3.5 40 mhz t chcx high time 10 ns t clcx low time 10 ns t clch rise time 10 ns t chcl fall time 10 ns rom verification characteristics symbol parameter min max unit 1/t clcl oscillator frequency 2.5 40 mhz t avqv address to data valid 48t clcl t elqv enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl
is80c51 is80c31 40 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi t lhll ale t avll t llpl t plph t pliv t llax t plaz t pxiz t pxix a7-a0 instr in a7-a0 t lliv t aviv psen port 0 port 2 a15-a8 a15-a8 t lldv t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl t avdv psen port 0 port 2 ale rd data in a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t rlaz t rldv t rhdz t rhdx t rlrh figure 29. external program memory read cycle figure 30. external data memory read cycle timing waveforms
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 41 mc003-1d 11/19/98 issi t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl psen port 0 port 2 ale wr data out a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t qvwx t whqx t wlwh instruction ale clock data out data in t xlxl t xhqx t qvxh t xhdv t xhdx valid valid valid valid valid valid valid valid set ti set ri 78 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 figure 31. external data memory write cycle figure 32. shift register mode timing waveform
is80c51 is80c31 42 integrated silicon solution, inc. 1-800-379-4774 mc003-1d 11/19/98 issi 0.45v vcc ?0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ?0.1 p1.0-p1.7 p2.0-p2.3 data out address port 0 p2.7 t ehqz t elqv t avqv note: 1. ac inputs during testing are driven at vcc C 0.5v for logic 1 and 0.45v for logic 0. timing measurements are made at v ih min for logic 1 and max for logic 0. vcc - 0.5v 0.45v 0.2vcc + 0.9v 0.2vcc - 0.1v figure 33. rom verification waveform figure 34. external clock drive waveform figure 35. ac test point
is80c51 is80c31 integrated silicon solution, inc. 1-800-379-4774 43 mc003-1d 11/19/98 issi integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 fax: (408) 588-0806 toll free: 1-800-379-4774 http://www.issiusa.com issi ordering information commercial temperature: 0 c to +70 c speed order part number package 12 mhz is80c51-12pl plcc is80c51-12pq pqfp is80c51-12w 600-mil plastic dip 24 mhz is80c51-24pl plcc is80c51-24pq pqfp is80c51-24w 600-mil plastic dip 40 mhz is80c51-40pl plcc is80c51-40pq pqfp is80c51-40w 600-mil plastic dip 12 mhz is80c31-12pl plcc is80c31-12pq pqfp is80c31-12w 600-mil plastic dip 24 mhz is80c31-24pl plcc is80c31-24pq pqfp is80c31-24w 600-mil plastic dip 40 mhz is80c31-40pl plcc is80c31-40pq pqfp is80c31-40w 600-mil plastic dip ordering information industrial temperature: C40 c to +85 c speed order part number package 12 mhz is80c51-12pli plcc is80c51-12pqi pqfp is80c51-12wi 600-mil plastic dip 24 mhz is80c51-24pli plcc is80c51-24pqi pqfp is80c51-24wi 600-mil plastic dip 40 mhz is80c51-40pli plcc is80c51-40pqi pqfp is80c51-40wi 600-mil plastic dip 12 mhz is80c31-12pli plcc is80c31-12pqi pqfp is80c31-12wi 600-mil plastic dip 24 mhz is80c31-24pli plcc IS80C31-24PQI pqfp is80c31-24wi 600-mil plastic dip 40 mhz is80c31-40pli plcc is80c31-40pqi pqfp is80c31-40wi 600-mil plastic dip

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